1. Field of the Invention
The present invention relates to power consumption of integrated circuit designs such as circuits used in hearing aids. More particularly, the present invention relates to generating a lower voltage from a higher voltage and regulating it to a fixed programmable voltage above a reference to achieve a reduction in power consumption.
2. Background Art
Today""s integrated circuit industry has produced a class of devices which operate from a relatively low voltage power source with relatively low power consumption. Most known integrated circuit families require an approximately five volt power source to operate properly. Three volt devices are becoming increasingly popular. The reduction in power source voltage requirements reduces the current drawn by the CMOS circuit. In other words, devices which operate at 2.7 volts are more readily adapted for use with power sources such as batteries than devices which operate at five volts. For most battery technologies, batteries which produce 2.7 volts are smaller and simpler than batteries which produce higher voltages. Since one goal in the design of small voltage circuits is to maximize their usefulness with power sources with limited capacity, it is highly desirable to minimize current consumption of each circuit.
Various devices require operation with low power consumption. For example, hand-held communication devices require such low power consumption and, in particular, portable medical devices require low power capabilities. With respect to portable medical devices, for example, digital signal processing-based hearing aid devices are required to operate with a very low power consumption to increase battery life and device longevity.
Generally, such low power devices are designed using complementary metal oxide semiconductor (CMOS) technology. CMOS technology is generally used because such technology has the characteristic of substantially zero xe2x80x9cstaticxe2x80x9d power consumption and very low dynamic power consumption.
The power consumption of CMOS circuits consists generally of two power consumption factors, namely xe2x80x9cdynamicxe2x80x9d power consumption and static power consumption. Static power consumption is only due to current leakage as the quiescent current of such circuits is zero. Dynamic power consumption is the dominant factor of power consumption for CMOS technology. Dynamic power consumption is basically due to the current required to charge internal and load capacitances during switching, i.e., the charging and discharging of such capacitances. Dynamic power (P) is equal to: 1/2CVDD2F, where C is nodal capacitance, F is the clock or switching frequency of each gate output node, and VDD is the supply voltage for the CMOS circuit. As can be seen from the formula for calculating dynamic power (P), such dynamic power consumption of CMOS circuits is proportional to the square of the supply voltage (VDD). In addition, dynamic power (P) is proportional to switching or node switching frequency (F).
In accordance with the formula for dynamic power consumption, it has been effective conventionally in CMOS integrated circuit designs to scale down the supply voltage for an entire device (e.g., hybrid) or integrated circuit (IC), i.e., operate the circuit at low supply voltages, to reduce power consumption for such designs.
FIG. 1 represents a graphical illustration of relative gate delay versus supply voltage for CMOS circuits. The circuit logic delay increases drastically as the supply voltage is reduced to near the threshold of the N or P devices, as represented by delay line 12 and threshold voltage line 14. As the supply voltage is decreased, such energy consumption is reduced by the square of the supply voltage as is shown by relative power line 16. Therefore, considerable power can be saved by lowering the voltage to logic circuits to the lowest possible voltage. The lowest voltage must be where the logic can function reliably for the task at hand.
FIG. 2 is a flow diagram illustrating a conventional voltage down pump 22. Although pump 22 provides a mechanism for setting a lower voltage 24 from a higher voltage 26, such pumping action may set a voltage below the threshold of a digital circuit, thereby rendering the digital circuitry inoperable.
Therefore, a need exists for an apparatus and method for regulating a programmable fixed voltage above a CMOS device threshold to keep the gate delay constant as temperature and process variations change. Such a circuit should be able to supply a stepped down regulated voltage for all pertinent digital circuitry. Using a lower voltage that is kept relatively constant as the battery voltage drops saves considerable power.
A regulated voltage down pump circuit comprises a reference generator circuit receiving a voltage. P channel and N channel device voltage thresholds are measured and compared. A first reference voltage is generated using the largest voltage threshold. A second reference voltage is generated an amount (which may be programmable) above the first reference voltage. The second reference voltage is compared with an output voltage. When the output voltage is less than the second reference voltage, a clock signal is sent to a voltage pump circuit that generates and pumps up the output voltage to the reference voltage. The pumped voltage at the second reference is then used for logic circuits at reduced power and nearly constant gate delay over voltage, temperature and process variations.